Design and Implementation of Low Power Digital Fir Filter Based on Low Power Multipliers on Xilinx FPGA

Authors:D. SUDHAMS REDDY, D. SURESH KUMAR

1759-1766

Quantization Noise Suppression in Fractional PLLs

Authors:V.VENKATA SIVA MOULI, J.RAVI

1767-1776

Efficiently Providing Data Confidentiality in Cloud

Authors:T.BHASWATHI BRAHMINI, T. SUNEETHA RANI

1777-1781

Security based CBRT in Mobile Ad-Hoc Networks

Authors:P.V.SOWMYA, C.H.NAGARAJU

1782-1788

A Reputation Check Strategy for Mitigating Routing Attacks in Manet’s

Authors:K. ARUNKUMAR

1789-1794

FPGA Based Area Efficient Median Filtering for Removal of Salt-Pepper and Impulse Noises

Authors:G.NEERAJA, S. DEEPIKA

1795-1804

Boot Strapping by Ontologies for EMR Semantic Search Services

Authors:A. NAGA SREENIVAS

1805-1810

FPGA Implementation of a Costas Loop for Wireless Communication

Authors:PRABHAKAR.R, RAVIKUMAR.P, B.MURALIDHAR NAIK

1811-1827

Application of Facts Devices in Disturbed Power Systems Modeling, Interface

Authors:D.KEERTHI PRIYA, M.BHASKAR REDDY

1828-1837

MEMS Accelerometer based Non-Specific – User Hand Gesture Recognition

Authors:M.LAVANYA, P.SURESH BABU

1838-1843